1. Field of the Invention
The present invention generally relates to computer systems. More specifically, the present invention relates to the control of a receive strobe in a computer circuit.
2. Description of the Related Art
Speed has always been an important factor in measuring the performance of a computer system, and speed depends, among other factors, how fast a central processing unit (CPU) can perform mathematical calculations, and how fast can data be retrieved from and stored into data registers.
Data are stored into the data registers or memory locations with help of a strobe signal. The data can be latched to their location by either the rising edge or the falling edge of a strobe signal. To achieve a high data rate, a Double-Data-Rate Synchronous Dynamic Random Access Memory (DDR-SDRAM or DDR) has been used. DDR differs from standard DRAM (SDRAM) in that it uses a separate strobe signal by which some or all of its data timing is referenced, and both the rising and the falling edges of the strobe signal are used to clock data into its destination. Using both edges of the strobe signal to transfer data thus doubles the amount of data transferred in a given time interval. This technique also allows higher data rates than standard single-data-rate SDRAM because the explicit strobe signal by which data is referenced can be used to remove some of the timing uncertainty present in the data receive path.
The strobe is a bi-directional signal, which is driven along with the data, and can be driven by either a controller or the DDR. If the controller wants to store (write) a data into the DDR, the controller drives the strobe to indicate the availability of the data on the data bus. If the controller is retrieving (reading) data from the DDR, the DDR controls the strobe to indicate the data is available on the data bus. This implies that neither the controller nor the DDR drives the strobe during time intervals between reads and writes. This results in the strobe signal being in a high-impedance state, usually at an indeterminate logic level, when not driven by either the controller or the DDR. Since the edges of the strobe are used to clock in receive data during reads, the propagation of this indeterminate level is troublesome. At this indeterminate level, the strobe may lead to an unintended edge at the receiving end which will latch an unexpected data.
Thus, a more precise system of blocking the reception of the strobe signal is needed at high clock speeds. It is to such a system and method that the present invention is primarily directed.
The present invention discloses a circuit and method for using the last falling edge of a receive strobe to block further reception of additional signals from the receive strobe.
According to one embodiment of the present invention a dedicated circuit that uses a phase signal, a receive enable strobe, a 2X clock signal, and a receive strobe from an I/O receiver to generate a new receive strobe for use by a data latch. The phase signal is a late clock signal, and the 2X clock signal is twice as fast as the system clock. The receive enable strobe is synchronous with the system clock.
The circuit includes several latches and ensures the last latch is gated asynchronously from the receive strobe and is clocked at the falling edge of the receive strobe. The output of this last latch is ANDed with the receive strobe and generates the new strobe for the DDR-SDRAM. This ensures the new strobe remains at a logic level that is unknown instead of undetermined, thus eliminating the unwanted latching at the receiving end.
The circuit according to the present invention changes the way the receive strobe is connected between a received data latch and the DDR-SDRAM. The receive strobe connection between the received data latch and the DDR-SDRAM is replaced by the circuit according to the present invention. The circuit receives the receive strobe from a bi-directional I/O buffer and generates a new receive strobe to a data latch delay system. The new receive strobe is used as a clock in the received data latch to clock the data from the DDR-SDRAM.
The circuit according to the present invention can be integrated inside of an application specific integrated circuit (ASIC) or inside of the DDR-SDRAM.
Other objects, features, and advantages of the present invention will become apparent after review of the hereinafter set forth Brief Description of the Drawings, Detailed Description of the Invention, and claims appended herewith.